1. Field of the Invention
Embodiments of the present invention relate to high performance memory based communications interfaces. In particular, embodiments of the present invention relate to methods and systems for reducing or eliminating the communications bottleneck between multi-processor computing systems and communication networks.
2. Description of the Prior Art and Related Information
The ever-growing need for computational performance is being satisfied by increasingly powerful commercial processors, and topologies that combine a plurality of processors around a communications network. To effectively utilize the power of such a system, especially where application software that is running concurrently on the processors needs to interact with each other, requires the use of an appropriate communications network. To date, the power of processors has outpaced the advances of communication network implementations, causing a bottleneck in the performance of applications.
Parallel applications typically interwork through an intermediary layer of software that abstracts the specifics of the underlying networks. These software layers may be, for example, a communications focused protocol stack (e.g. Transmission Control Protocol/Internet Protocol—TCP/IP) or a library (e.g. Message Passing Interface—MPI) which may include both communications and value added services. Communication network implementations include network switching (which transmit network level entities to their destinations), network endpoint processing (which provide the network transmit and network receive functions on behalf of the host) and communications endpoint processing (which provide efficient writing and reading of data to/from memory, interface to/from the network endpoint processors, synchronization of the data with workloads, and providing quality of service guarantees to workloads).
The computational domain is primarily designed for functional richness (support for Operating Systems—OS, Libraries, Application Program Interfaces—API's, multi-threading etc), whereas the communications domain is primarily designed for simplicity, throughput and low latency. The computational domain is typically software based and the communications domain is primarily hardware based (although this is not always the case). The interfacing of these two domains may cause performance bottlenecks.
Conventional methods and systems for addressing the interface between the computational and communications domain have been characterized by a number of initiatives for high-performance networking. The most dominant approach is Ethernet. Ethernet solutions include Ethernet switches and host NICs (Network Interface Controller) that may include switch endpoint and communications endpoint functions. Ethernet communications solutions have evolved with respect to bandwidth (as of this writing, [10 Gbs Ethernet] 10GE is emerging and the Institute of Electrical and Electronics Engineers [IEEE] is looking at 40 Gbs Ethernet rates as a next step), and with respect to functionality. Ethernet networks use a NIC to map frames in main processor memory to the network. They incorporate a Direct Memory Access (DMA) controller, but this typically is limited to sending a frame (or packet) at a time for transmission to the network. Ethernet with Hardware Offload Acceleration extends the Ethernet capability by adding support for TCP and RDMA (Remote DMA) protocols on top of the core Ethernet. Importantly, this protocol still only sends one fame (or packet) at a time. The latest NICs have included TCP offload, Direct Memory Access (DMA), Remote Direct Memory Access (RDMA), and Internet SCSI (Small Computer System Interface) (iSCSI) hardware support. Software maps the services to standards based TCP communications.
Asynchronous Transfer Mode (ATM) has a variety of NIC's and Switches, with software to adapt standards based interfaces to the ATM network. ATM is not being evolved as a significant computer interconnect technology. With ATM, the frame is typically transmitted as a packet to the ATM NIC where it is stored in local memory and Segment Assembly and Reassembly (SAR) functions are performed.
Infiniband is a computer industry initiative aimed to provide high performance interconnect. Infiniband is a whole cloth solution providing, switches, Host Channel Adapters, interface software and standards based software mapping. Indeed, Infiniband defines an interface between computer memory and a high performance network. The Infiniband Architecture (IBA) includes an industry defined specification that defines the Meta Architecture of Infiniband. At the architecture specification level, there are differences in the methods used to map the data queues to applications. The implementation of IBA has been limited due to a lack of acceptance of this architecture outside of high performance applications. There are a number of vendors that provide Infiniband hardware and software components.
There are also a number of other proprietary hardware interface devices and switches that, when combined with appropriate software, may be used for computer communications. Such communication switches are typically used for data communications and have a rich set of “quality of service” attributes. They are typically packet oriented and the interface device receives packets over an electrical bus and the device performs internal segmentation and storage in local memory.
Due to the shortcomings of the existing solutions, more efficient systems and methods need to be developed to reduce or eliminate the communications bottleneck between multi-processor computing systems and communication networks.